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informedperson

11 karma · joined March 21, 2017

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informedperson··on AMD Ryzen Machine Crashes on a Sequence of FMA3 Instructions
True, my mistake.

(While it doesn't apply for this specific example, it's still the reason why one generally will see microcode-fixed errata go away rather quickly, independently of BIOS updates)

informedperson··on AMD Ryzen Machine Crashes on a Sequence of FMA3 Instructions
Desktop parts have no dedicated AVX clock (however, their base vs. all-core turbo pretty much does the same thing), while server SKUs (Socket R3 and later) basically have two distinct clocking ladders, one for non-AVX code and one for AVX code (the "mode switch" quantum is rather coarse, on the order of one millisecond). So both base clock and maximum turbo clocks are lower in AVX code compared to non-AVX code.

As usual, actual achieved clock speeds depend on thermal performance and are not fixed. If cooling is completely insufficient, the clock frequency will drop below base clocks, i.e. thermal throttling.

To clarify: This isn't a secret, but part of the specs and even in some Intel slides. (However, platform and processor specs, even at a basic (product D/S) level, tend to be a rather lengthy read, so most do away with reading all that).

informedperson··on AMD Ryzen Machine Crashes on a Sequence of FMA3 Instructions
Windows 7 and later distribute and activate microcode updates through Windows Update.
informedperson··on AMD Ryzen Machine Crashes on a Sequence of FMA3 Instructions
A power issue would also plausibly explain why disabling SMT avoids the problem, since disabling SMT powers off a bunch of stuff (a whole thread context does need a bit of power), and, in a multi-threaded scenario, tends to reduce core usage thereby reducing average (! so likely not relevant) power draw as well.
informedperson··on AMD Ryzen Machine Crashes on a Sequence of FMA3 Instructions
Well doing that tends to halve throughput for ALU-dense code, but obviously saves a bit of die space and more importantly reduces peak power draw, which has to be supported by the metallization on the chip.

AVX2 might have also been just a bit too late to be integrated outside the microcode.

informedperson··on AMD Ryzen Machine Crashes on a Sequence of FMA3 Instructions
You're not wrong - the Vcore boost when both AVX pipes are powered up causes increased dissipation, but a large part of that is also caused by ... well, AVX processing huge amounts of data.

For similar reasons server processors (Xeon E5, E7 series) throttle the core clock in AVX "mode".