ChipLink is indeed routed out to the FMC. The demo during FOSDEM was done with a FPGA card attached to the FMC which then drove additional peripherals.
Jack, SiFive
19 karma · joined June 27, 2017
Jack, SiFive
The reason for the large RAMs and microSD card is specifically to help software developers. That's who the board is for until we can drive the cost down even further for even more folks.
-Jack Kang, SiFive
RISC-V is a free and open instruction set architecture (ISA). People can go ahead and build open-source implementations, closed-source implementations, licensed implementations. This is very different than ARM, where you can only buy implementations from ARM, or if you happen to be one of a handful of selected companies with an ARM architectural license (which costs $$$$$), you can build your own implementation, but they still have to meet certain specifications as dictated by ARM. People can freely implement RISC-V processors, extend them, and play around with it. We think RISC-V has a big potential to unleash innovation. As a matter of fact, we believe this is the prerequisite.
SiFive has made the RTL open-sourced that went into FE310. We think this is a big deal, because other SoCs don't open-source their RTL.
On your questions: 1) We are providing FE310 samples to folks who ask us for them at info@sifive.com
See our past forum posts for similar requests: https://forums.sifive.com/t/assistance-getting-in-contact-wi... https://forums.sifive.com/t/e300-on-the-market-other-sbc-s-w...
2) We do provide both versions, just as you recommended. SiFive continues to maintain the Rocket repository at https://github.com/freechipsproject/rocket-chip
We intend to continue to maintain this core and ensure it's compatible with any updates to the RISC-V specification.
For commercial customers who do not want to utilize rocket-chip, we are providing them with other options.
-Jack (from SiFive)