keyi

1. Yes we are a great fit for edge ML inference, but we are also great for DSP and other, general-purpose application logic.

2. Our chip has an integrated memory & integrated non-volatile storage that are shared across the tiles in our architecture.

3. We agree, RF applications are very interesting and are a great fit for our architecture in a lot of cases

4. It's hard to say what the energy savings would be versus that specific chip without doing some benchmarking. We have measured 10-100x improvement in energy consumption against several very competitive Arm implementations that we've tested and I'd expect to see a similar advantage.

> What do you mean by "the" compiler for our chip?

We are designing a dataflow general-purpose processor that can directly executes the dataflow graph from the compiler.

> Is this a compiler backed like LLVM which generates efficient machine code, that other languages can target?

The compiler itself takes LLVM as the input, so if your framework can output LLVM, you should be able to target our compiler backend and hardware. We had a prototype working with Rust as well. The compiler does not however use LLVM to produce the machine code on our hardware -- custom mapper/assembler and linker is used to produce the machine code that runs on the hardware.

> what kind of resources do you have that I could read about targeting your hardware?

We have published a couple papers about our compiler and hardware design: https://www.efficient.computer/media. Unfortunately we don't have a concrete plan to open up the compiler yet. Please stay tuned!

Have you compared the result with latest image compression formats, such as AVIF[0]?

[0]: https://aomediacodec.github.io/av1-avif/