mbad0la

Hmm...let's hope that this open-source tool becomes a better alternative to other proprietary softwares. Would be amazing for the academic community.

Thanks for the references though!

This is so cool!

I'm so clueless about a lot of things! :p

Can you provide some reference link to systemVerilog?

I think it's probably a clichéd Js Dev thing :p

But one of the reasons might be because I would like the person going through my code to easily understand it without much problems.

It's more about perspective I suppose and the requirements of the project.

Couldn't agree more! Someone has already suggested me some cool libraries that I might be able to use. Visualisation is on the agenda definitely.

Yeah, using events do offer an amazing async behaviour.

Thus,the I/O arguments of every hardware component are extensions to EventEmitter, resulting in quite an amazing simulation.

True. I had VHDL in my 5th semester and it was easy to get started with it.

Let's hope the community shows some interest in my efforts to make this library the best of both worlds - verbosity with action :P

Oh these were great!

I didn't know about them though. My project's inspiration is due to the fact that I love JS and had a computer system architecture course wherein I learnt VHDL.

I felt that the NodeJS Events API could probably help me simulate a `signal` driven system and thus, I started experimenting :)

I will certainly give it a look :)

Yeah, I haven't had the opportunity to use Verilog but it does seem very readable!

I want to kind of give this library a similar direction. It's in its infancy at the moment :P

Cool!

So we can implement a descriptive component doing something similar on the same lines.

But I kind of thought of pushing more for a `functional behaviour`. Hence I used the existing AND-Gate to build the Four Input AND-Gate.

I should probably put the descriptive component on the README as well