22 karma · joined October 8, 2023
ax is a 2 bit register initialized to 0.
100: add 1 ax
101: jmp 100
ax is 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3
0 is compared to 1, 1 is compared to 3, 3 is compared to 2, 2 is is compared to 2, wait, that's an infinite loop...
I compiled it, ran ./vitalixprng &> output.txt and then ran Detect It Easy's entropy measuring tool on output.txt to give me around 3.41 bits of randomness per 8 bits.
It outputs 2 hex characters (hex character = half byte = 4 bits) per clock cycle.
It gives out pseudorandom output that looks like this:
28595827262617506937569201755869372950673748294758392
Edit: My dad says that Ukraine has such a system where 40% or more, cool.
// It was picked with a dice roll.
How would you improve my FPGA? I have two directions that I could take my FPGA architecture such as adding analog Logic Blocks and adding beamforming LUT interconnect.
Can you explain how you would go about getting an MVP manufactured?
I raised $372.03 for my FPGA chip on my profile and I've only sketched out a rough mock prototype of what I want the architecture to be.
So far, it works with any amount of silicon defects, can be up to the size of a silicon wafer, and the larger it is, the more it can reconfigure itself in parallel, which is directly proportional to its size growth.
I'm going to install Solus OS / Solus Linux soon, had a good first impression with it's package manager, which claims to be reproducible but not like nix or guix are.