Can you share more about how you are prompting to disable sycophancy?
47 karma · joined January 3, 2024
Can you share more about how you are prompting to disable sycophancy?
Hyper even got acquired by tableau a few years ago
Led to a few happy discoveries of compiler optimizations in Rust.
I think for someone who has no exposure to it before, its quite dense (perhaps long wasn't the best choice of wording)
Also, I've been meaning to read The Art of Multiprocessor Programming. I've heard great things about it!
I added in a note about the ABA problem but perhaps you're seeing a cached version of the post.
>I guess the missing bit is that beyond the hardware fences you have the hardware cache coherency protocol that makes sure that a total order of operations always exist once load and stores reach the coherence fabric.
Can you explain more about this?
Assuming that the memory barrier is syncing across a single variable (in this case ready), why would it be correct to think of it as two separate barriers? If it were correct to think of it as two separate barriers on two separate threads, wouldn't there need to be some form of synchronization or linkage between the two barriers themselves so that memory barriers can be coupled together?
For instance, if I had release-acquire models on two variables, ready and not_ready, using separate barriers as representation might look something like this
```
Thread 1 Memory Thread 2
--------- ------- ---------
| | |
| write(data, 100) | |
| -----------------------> | |
| | |
| ====Memory Barrier====== | |
| store(ready, true) | |
| -----------------------> | |
| ====Memory Barrier====== | |
| | |
| ====Memory Barrier====== | |
| store(not_ready, true) | |
| -----------------------> | |
| ====Memory Barrier====== | |
| | |
| | ===Memory Barrier======= |
| | load(ready) == true |
| | <---------------------- |
| | ====Memory Barrier===== |
| | |
| |.===Memory Barrier======= |
| | load(not_ready) == true|
| | <---------------------- |
| | ====Memory Barrier===== |
| | |
| | read(data) |
| | <---------------------- |
| | |
```Now, how does the processor know which memory barriers are linked together? I ask because without understanding which barriers are linked together, how is instruction re-ordering determined?