ruik

There seems to be some bits in Intel PCH chipset datasheets for that: Power Button Override Period (PBOP): This field determines, while the power button remains asserted, how long the PMC will wait before initiating a global reset. Encoding:

000b - 4 seconds

001b - 6 seconds

010b - 8 seconds

011b - 10 seconds

100b - 12 seconds

101b - 14 seconds

Others - Reserved

This bit is reset by DSW_PWROK de-assertion. (edited formatting)

The ACPI specification says: Additionally ACPI defines a fail-safe Off protocol called the “power button override,” which allows the user to initiate an Off sequence in the case where the system software is no longer able to recover the system (the system has hung). ACPI defines that this sequence be initiated by the user pressing the power button for over 4 seconds, at which point the hardware unconditionally sequences the system to the Off state. This logic is represented by the PWRBTN_OR signalcoming into the sleep logic.

Well I believe it is the ID for the x86 "Corporate Entity Other Than Intel/AMD", as mentioned https://www.phoronix.com/news/x86-Opcodes-Not-AMD-Or-Intel and here https://www.phoronix.com/news/16-Tile-32-Tile-AMX-Performanc...

Maybe better link https://fahrplan.events.ccc.de/congress/2024/fahrplan/schedu...

That blast from the past and welcome to the 80's ! The 0x87 BIOS service is used to perform the memcpy() from real mode. You might think it is just 3 arguments! But not in that good old days of 1987++ it was all much more convoluted fun! The API has so strange format because it tells you to construct two segment descriptor entries including correct segment attributes. The structure of that buffer is a hack that allows BIOS to create more entries internally (SS/CS? descriptors likely) and use whole buffer as a new GDT which will be used for a copy in protected mode stub. So your destination on SI+0x18 and source SI+0x10 are in fact two GDT entries which BIOS will just use for REP MOVSD/MOVSW. And because you are on 386+ CPU, yes you can use full 32-bit address (in SI+0x17/SI+0x1E) If you are wondering about the detailed format, check data segment descriptor format in AMD or Intel documentation. The max size to copy in CX reg is 0x8000*2 bytes, but this is likely due to the 80286 segment limit which was 64K. It may just work on 386 with 128K, but I would not count on it. Keep the SI+0x16/SI+0x1D zero -> Don't touch D/B bit nor the G bits. You can consult Ralf's brown interrupt list for further details about this INT 0x15 AH=0x87 call. Rudolf

Please see the original blog post - https://www.righto.com/2023/07/8086-pins.html why this is even linked to the adafruit website?

34C3 - The Ultimate Apollo Guidance Computer Talk - https://www.youtube.com/watch?v=xx7Lfh5SKUQ

Please also check curious marc youtube channel where you will find almost all of mentioned adventures!

A nice test would be to compare a "cpuid -1 -r" before and after applied microcode updates. To check if new bit(s) is set somewhere.

Worth might be to check if IA32_ARCH_CAPABILITIES contain new bits set as well on some platforms which would indicate they are not affected. Via the NO_xxx flag.

Thank you very much, I missed that. Probably due to 0x21 instead of 21h. Makes sense, they just need to tell AMD not to put ever anything on leaf 0x21, as the 0x21 leaf is handled by the VMM, and will return something else.