There are tons of other practical problems. The HLS generated verilog is name mangled. This makes it really hard to generate all the various control files you need to run the EDA flow, the software that assists in turning verilog into manufacturing files. If you have a super stable design, like a codec, then you can deal with it because it’s basically a waterfall development cycle. But if you have a design whose requirements are changing as you develop it, like most things. HLS doesn’t fit into the existing organizational structures and you’ll end up with a less optimal circuit.