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SystemVerilog is even cleaner. And those built-in simulation primitives....damn, I loved my SV classes.

I'm so clueless about a lot of things! :p

Can you provide some reference link to systemVerilog?

Here is a link to the standard:

http://standards.ieee.org/getieee/1800/download/1800-2012.pd...

There is an open source compiler which can compile the hardware description subset of system verilog to c++ called verilator:

http://www.veripool.org/wiki/verilator

It was originally developed to verify processor designs at DEC (Alpha etc.).

Unfortunately all the other features of system verilog are onl y implemented in commercial tools. I believe the Xilinx Vivado tools support most of it, the others are not really affordable if you are not at an academic institution (Modelsim/the Synopsis tools).

In this website[0], you can compile and play with systemverilog using Synopsys' vcs.

[0] - https://www.edaplayground.com/

Hmm...let's hope that this open-source tool becomes a better alternative to other proprietary softwares. Would be amazing for the academic community.

Thanks for the references though!

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