Going much smaller than we have right now, and you run up against some exotic issues--if you decrease the dielectric thickness, you run the risk of break down between the gate and source/drain under normal operating conditions. Your steady current rating also drops dramatically if the other feature sizes are decreased. I would probably say a 3 atom MOSFET is not possible, since at that scale you can't really have an effective dielectric between the atoms, and the conductors connected to the "single-atom terminals" will have a bulk effect on the behavior.
> if you decrease the dielectric thickness
This is why people are moving away from planar transistors to "FinFets" and eventually having an "all around gate"
3nm (or any "node" measurement) is not a measure of the entire transistor, only of the smallest feature size.
What do you mean by "feature size"?
A semiconductor is made of multiple surfaces/areas. Their lithographic process allows to have some at 3nm in size, but a transistor can be a sum of many parts.
A very rough approximation would be to describe a wind-up watch (processor) by the smallest tooth of the smallest gear (component of the transistor)