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RISC-V is an ISA. However, Berkeley BOOM is a microarchitecture, an out-of-order superscalar RISC-V core. It is synthesizable and parameterizable. While BOOM is primarily ASIC optimized, it is also usable on FPGAs.

https://boom-core.org/

But what I'm really interested in is which adder modern microarchitectures use.

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BOOM uses the rocketchip ALU, which uses the Chisel `+`, which probably compiles down to the verilog `+`, which probably gets synthesized to the appropriate width adder in the standard cell library of the vendor (e.g. TSMC or Xilinx). So for synthesized microarchitectures, it isn't determined in the RTL.

As far as I know it's still good old carry lookahead, just with a lot more bits. The advances have come from multiplication and especially division; addition was figured out early on.

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