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Comment by Nokinside | Hacker News Reader

The number 7nm 5nm etc. ceased to refer anything physical after the technology moved on from planar transistors. Now it's just a commercial name for a generation.

The most important dimensions are the gate pitch and metal pitch. For TSMC's 7nm process they are something like 60 and 40 nm and go down in the future to something like 30 nm and 20 nm in the 2nm process. Fin width might be the closest thing to commercial name.

They are not even comparable across companies. For example, TSMC 7nm process technology has 91 MTr/mm², Intel's 10 nm prosess technology has 100 MTr/mm². Samsung 10nm has 52 MTr/mm². (MTr/mm² refers to millions of transistors per mm²).

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For perspective, 2nm is approximately how much your fingernail grows in the time it took to read this sentence.

(3.47mm per month)/(30 * 24 * 60 * 60 seconds) = 1.33nm/second

That's a fun factoid to know. Thanks

What's the MTr/mm2 for TSMC 5nm? 2nm?

EDIT: looks like 173M for 5nm. https://en.m.wikipedia.org/wiki/5_nm_process

TSMC 5nm is 170 MTr/mm2. Then it's goes above 200 MTr/mm2

Intel 7nm is something like 200 MTr/mm2.

Any news on 2nm?

Very interesting, thank you. So we're basically not nearly as close to "true" 7nm as I thought? Do companies like TSMC already have a plan as to how to deal with "true" 7nm or is a lot more research still needed?

According to this video using an electron scanning microscope on amd and Intel chips, the “7nm” or “10nm” number does not measure anything, and is effectively a process version number for marketing. From memory there is no single number for measuring transistors or efficiency, transistor density is useful, but it doesn’t tell you the performance or power usage.

https://youtu.be/1kQUXpZpLXI

Moore's law always was an economic roadmap. Everything in the semiconductor industry is (was) planned around the transistor density doubling every two years, from hardware investments, to market segmentation, to microarchitecture design, to software optimizations. So I think it makes sense that they go on with pushing transistor density from generation to generation, and convey it to the public using names it is already familiar with.

It's right that power has severely limited performance despite increasing the transistor density lately. Maybe we'll once again get better with adiabatic computing?

Both performance and power usage are physically functions of transistor density. Assuming the apples-to-apples comparison of similar transistor counts, operating TDPs, and processor designs.

For whom? Surely the people ordering chips know the truth.

>Do companies like TSMC already have a plan as to how to deal with "true" 7nm or is a lot more research still needed?

If you will forgive the expression. Yes and No.

Yes in that TSMC has ideas / plans scaling all the way to 0.8nm, targeting 2030. That is only a few steps above what you described as true 7nm.

No in that no one knows if it will work. We know Quantum Tunnelling will hit some day, some where, some how, at some percentage.

Remember you are talking about leading edge Semi-Conductor manufacturing. Nothing like this has ever been done before.

It is a bit like telling me 5G today was possible when I was researching on first gen 3G two decades ago. If you describe to me with theory I will have properly said yes..... but it is hard to imagine how it will actually be implemented.

Technically it’s figured out. Gate-all-around has been experimentally demonstrated at pitches less than FinFET. The primary problem is, who is going to pay it. The economics are very tough at these 1s of nm nodes but hopefully that’s only a transitory problem.

You are talking about GAA at 2nm, I was talking about sub 1nm ( Node naming ) Tech. Which the OP was referring to "true" 7nm or Gate pitch / metal pitch at sub 7nm. We are still quite far away from figuring those out.

But yes, I agree the economics model is tough as I have been stating on various forums for years. That is part of the reason why we see Semi-conductors consolidation, like Marvell, Broadcom.

My best guess is that some time in 2026/ 28 we might have to stretch the cycle to three years instead of two. Giving more time to amortised those cost. But HyperScaler Cloud Market seems to be not limited by any R&D funding so I am actually quite optimistic we could see the current 2 year cadence all the way to 2030. Anything beyond is just too hard to predict or infer.

To make transistors smaller, and not just draw them with finer resolution, the industry will need a new way of controlling the channel. FinFET got us here. Most likely gate-all-around will be the technique that gets the “true” geometries smaller.

https://en.m.wikipedia.org/wiki/Multigate_device#GAAFET

That's interesting, I saw a hobbyist photo lithography setup the other year that was able to etch metal with a resolution of 20nm.

State of the art non EUV photo lithography uses light with a 193 nm wavelength. 20nm is significantly below that which would imply usage of highly advanced lithography techniques like multiple patterning. A chip manufactured with a 20nm resolution would involve dozens of masks which were created through electron-beam lithography. Just the mask set alone would cost millions of dollars.

The only hobbyist that I am aware of used a pretty nifty mask less technique but the resolution doesn't come close at all. I think you just mixed up your units.

That's really not possible. 20um probably. Micro not nano.

Well, nano would be achievable via e-beam lithography, but photolithography is another beast: I'm pretty sure you need EUV at that size, with special (expensive) lenses that do not absorb the UV.

Can't edit this, what I saw was definitely um and not nm.

I recall this but don't remember seeing anything smaller being posted. Sub 100nm for a hobbiest would be pretty awesome. https://youtu.be/YAPt_DcWAvw

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