It used to be that it was a linear scaling factor. So if you moved from, say, 40nm to 20nm, you'd see a 4x increase in transistor density. In the early days of VLIW scaling (roughly from 45nm and up), that really did work by just "making everything smaller". And in that world, the smallest thing was generally the size of the middle/active region of the transistor on top of which the gate sat, so the "gate length" (which is actually the *width* of a resist line that crosses the transistor) became the standard.

But then they started having to cheat: you can take a big transistor and "fold" it vertically to be smaller but still have the same gate area, etc... The actual feature sizes may not have changed much but you have the 2x density increase, so you name your new node "32nm" even though the actual width of the gate feature when seen from above didn't change, etc...

But then somewhere around 10nm everyone just gave up and started handing out random numbers. TSMC's 3nm process is not remotely a 2x density increase over 5nm, for example.