SemiTom

Another good resource for moving to GAA FETs https://semiengineering.com/moving-to-gaa-fets/

The apparent driver here isn’t about AMD wanting to get into the FPGA business. The real motivation appears to be a combination of platforms and programmable chiplets. There are two problems that programmable chips address https://semiengineering.com/amd-wants-an-fpga-company-too/

Interesting to see where this is gaining traction and where the challenges are https://semiengineering.com/where-risc-v-is-gaining-traction...

According to this article https://semiengineering.com/china-speeds-up-advanced-chip-de... they are into advanced chip development:

-SMIC is shipping 14nm finFETs, with a 7nm-like process in R&D. -Yangtze Memory Technologies (YMTC) recently entered the 3D NAND market with a 64-layer device. A 128-layer technology is in R&D. -ChangXin Memory Technology (CXMT) is shipping its first product, a 19nm DRAM line. -China is expanding into compound semis, including gallium nitride (GaN) and silicon carbide (SiC). -China’s OSATs are developing more advanced packages.

There are challenges but work is on the way, transitioning to gate-all around FETS (GAA Fets) https://semiengineering.com/making-chips-at-3nm-and-beyond/

An expanding attack surface in hardware, coupled with increasing complexity inside and outside of chips, is making it far more difficult to secure systems against a variety of new and existing types of attacks https://semiengineering.com/hardware-attack-surface-widening.... Per Paul Kocher “AI will help attackers in a number of ways, where behaviors that used to be unique to humans can now be automated in ways that are lot harder to distinguish from humans"

Hi there, I'm seeing more and more remote roles that our posted on our semiconductor publication site for engineers due to the talent shortage. If you dig into some of the roles, it indicates flexible locations. https://semiengineering.com/jobs/ . Best of luck

It's one of the biggest engineering problems in the last 10 years due to sensory input issues, dealing with the unexpected behavior of outside influences and you have to have the mechanical and software components that the first two components give the commands to, and can then faithfully execute them https://semiengineering.com/challenges-to-building-autonomou... and https://semiengineering.com/more-data-more-problems-in-autom...

Single-source ISAs of the past relied on general industry verification technologies and methodologies, but open-source ISA-based processor users and adopters will need to review the verification flows of the processor and SoC https://semiengineering.com/will-open-source-processors-caus...

another good Youtube playlist for Architectures from Semiconductor Engineering https://www.youtube.com/playlist?list=PL4RrBxLcT1nY9ugQ_V-1p...

Interesting to read Thomas Dolby's thoughts on music/technology interfaces--particularly with VR https://semiengineering.com/thomas-dolbys-very-different-vie...

https://semiengineering.com/5nm-vs-3nm/ TSMC’s 5nm technology is 15% faster with 30% lower power than 7nm. A second version of 5nm, due out next year, is 7% faster. Both versions also will use EUV.

FPGAs are getting larger, more complex, and significantly harder to verify and debug https://semiengineering.com/fpga-design-tradeoffs-getting-mo...

Scaling will continue in conjunction with packaging, but whether that’s Moore’s Law is debatable. The economics of traditional shrinking are gone. It now costs more per transistor at each new node. And the power/performance improvements have sharply diminished from pure scaling, probably into the range of 10% to 15% versus 30% to 50%. However, by combining architectural improvements (neural nets, moving memory closer to processors and vice versa, faster interconnects) and by stacking memory on die or embedded them in the same package, it’s possible to achieve orders of magnitude improvements in performance and power. This has been called More than Moore, and TSMC is now calling it More Moore.

Clean data is essential to good results in AI and machine learning, but data can become biased and less accurate at multiple stages in its lifetime—from moment it is generated all the way through to when it is processed—and it can happen in ways that are not always obvious and often difficult to discern https://semiengineering.com/where-data-gets-biased/

Big chipmakers are turning to architectural improvements such as chiplets, faster throughput both on-chip and off-chip, and concentrating more work per operation or cycle, in order to ramp up processing speeds and efficiency https://semiengineering.com/chiplets-faster-interconnects-an...

Scaling certainly isn’t dead. There will still will be chips developed at 5nm and 3nm, primarily because you need to put more and different types of processors/accelerators and memories on a die. But this isn’t just about scaling of logic and memory for power, performance and area reasons, as defined by Moore’s Law. The big problem now is that some of the new AI/ML chips are larger than reticle size, which means you have to stitch multiple die together. Shrinking allows you to put all of this on a single die. These are basically massively parallel architectures on a chip. Scaling provides the means to make this happen, but by itself it is a small part of total the power/performance improvement. At 3nm, you’d be lucky to get 20% P/P improvements, and even that will require new materials like cobalt and a new transistor structure like gate-all-around FETs. A lot of these new chips are promising for orders of magnitude improvement—100 to 1,000X, and you can’t achieve that with scaling alone. That requires other chips, like HBM memory, with a high speed interconnect like an interposer or a bridge, as well as more efficient/sparser algorithms. So scaling is still important, but not for the same reasons it used to be.

How and where data gets scrubbed will have significant consequences. While clean data is more valuable than dirty data (the mass of raw data collected by sensors), there is hidden value in those large masses of data. They can show broad trends and patterns that are not obvious in clean data, which is the modern equivalent of not seeing the forest for the trees https://semiengineering.com/data-vs-physics/

At the device level, variability remains a significant issue for all memristor types. Scaling feature sizes down is likely to make variability worse. https://semiengineering.com/integrating-memristors-for-neuro...

Some alternatives are neuromorphic, heterogeneous computing and advanced packaging. Neuromorphic relies on neural networks, and one of the interesting things there is lower accuracy computing to speed things up because you have a whole network of sensors to provide context and collective accuracy. Heterogeneous relies on different types of processors and memories scattered around one chip, which could include GPUs, APUs or even embedded FPGAs. Advanced packaging uses different chips packaged together and connected through bridges, interposers or in the case of monolithic 3D, TSVs between different metal layers. (Here's another link on the same site: https://semiengineering.com/big-changes-for-mainstream-chip-...)

These are definitely major shifts, not marketing. The difficulty in continuing Moore's Law/Dennard scaling at 7nm and below makes it imperative to use alternatives. Instead of 50% improvements in power/performance at each new node, it's now 20% max, and probably significantly lower in some cases.

good tech talk video page https://semiengineering.com/videos/

we just cancelled a long planned trip up to Canada because of the wildfires & smoke....

There are something like three dozen startups working on different chips that can speed up this whole process. The big question for all of these companies and their architectures is how flexible they will be for anything beyond a very specific implementation of an algorithm. This is particularly important in the AI/ML world because the algorithms are changing so rapidly. The challenge here goes well beyond the chip architecture. So if you think about the benchmarks for CPUs today, those can be blazing fast, but when you try them out on real applications they run a lot slower. Those differences may be magnified with parallel approaches. Different applications utilize different levels of parallelism with uneven performance improvements. It's not just how the processing is parsed, but also how effectively the results can be recombined after processing.

how about taking it one step further and aggregate the database of all hospital prices so we can filter and compare. better yet, single payer system overall

There are opportunities to be had but there is a fair amount of hype as well. https://semiengineering.com/blockchain-hype-reality-and-oppo...

Car forensics will be interesting. There will be data collected minutes/seconds before https://semiengineering.com/anatomy-of-an-autonomous-vehicle...

article says "Chips developed for computers and phones were designed to operate at peak performance for an average of two to four years of normal use. After that, functionality began to degrade"

It's not just about the CPUs or APUs, which generally have very high yield and long lifetimes. It's all the other chips. SSD begins exhibiting errors after extensive use. Other chips that are considered good enough are at the high end of their acceptable performance tolerances when they are included in devices, but the effects are additive. So the more chips running at the high or low end of what is considered acceptable, the more likely that problems will crop up over time.

The ecosystems that will be disrupted by self driving cars are vast https://semiengineering.com/giant-auto-industry-disruption-a...

Whatever the issues surrounding cryptocurrencies, their underlying blockchain networks have a remarkable record. https://semiengineering.com/blockchain-hype-reality-and-oppo...

Interesting perspective on speed up neural networks https://semiengineering.com/speeding-up-neural-networks/