If you get a chance check out his recounting of RIM rise and fall.
Edit: it seems he got it back :)
147 karma · joined November 8, 2014
If you get a chance check out his recounting of RIM rise and fall.
Edit: it seems he got it back :)
I was clearly wrong in that many people disagreed and found this to be an interesting and nontrivial subject.
Bend left -> torque to the right, bend right -> torque to the left. Here you have the basic ingredient for stability: the one torqueless angle is the bike going straight perfectly vertical wrt the ground, while any perturbation leads to a torque in the opposite direction.
I felt it was basic stuff maybe it's not?
Plus all the arguments about local storage failure being hard are moot because this is a distributed solution and the hardship of local storage reliability can be abstracted away almost completely.
Did you take your educated guess at that fraction?
I work on this project, feel free to ask anything.
-refresh period is more like 32-64ms
-refreshing is way (way) cheaper than streaming data out since you refresh an entire word line, and you do not pay io cost, which is a significant fraction of the cost of accessing dram.
BS: "going into production this year"
Possibly not BS: "going into production this year at 2x nam technology node with a y Gb part"
Many nvm memory technologies, including mram and PCM have been "in production" for quite many years, with << 1Gb parts on old technology nodes, that is.
Re the latency caveat I was suggesting BS spotting rules. You're right that this article did not claim the memory was faster than dram.
RE power consumption, it's true that it you don't use it an NVM will not consume power, yet that is not what people refer to when talking about power consumption. Can you quote a technology paper that shows lower than dram, or lower than flash for that matters, active power consumption? (The proper unit is W/GBps here)
-refresh power is on the order of milliwats per Gigabyte
-memory access is on the order of 0.1W per GB per second
For refresh power, let's face it: it's puny. Regarding the active power, I have yet to see anything (off chip and this size) that is better than that.
P.S. I did say active in my original post :)
Here's how to spot BS: first, the density claims are immaterial until they prove yield at a technology node same as dram's today. There are multiple billions investment between 180nm and high yield (and low mask count) 2xnm, no matter how cool is the new memory technology.
Second, speed claims must be explicitly about latency: flash bandwidth is as large as you want it, latency is ~100us (read). Even so, the moment anybody claims that latency is faster than Dram, you know they're feeding the hype and lying to you: dram latency does not depend on the memory technology, rather it depends on the array size. So an 8Gb chip of any memory technology that is fast enough, is likely to be just as fast as dram.
Third: power consumption. Dram's active power is as low as it gets, the memory cell in particular stores information with really little energy. The array interconnect and circuitry consume most energy and a different memory technology won't change that.
For a large fraction of the world's population time is not money...