rachitnigam

You can express full CPU designs in Calyx (in fact, we have) because it is a superset of a hardware description language. However, Calyx will probably not provide any substantial benefit in this case because there are not that many opportunities to optimize things.

The premise of Calyx is you're generating hardware designs from high-level code which has a lot more structure than arbitrary HDL code and the compiler will use that extra structure to automatically do optimizations that cannot be done over arbitrary HDL code.

Yeah, we've been able to compile entire neural networks like GoogleNet etc. through Calyx. See: https://calebmkim.github.io/files/pubs/src.pdf

HLS-like languages are an input to Calyx. For example, we're currently building a Vivado alternative using Calyx and the frontend there does the pipelining for us. Calyx then goes in and performs a bunch of other optimizations.

A big edge we have is that Calyx supports both statically-scheduled circuits (where the latencies of things are known) and dynamically-scheduled circuits (where latency is not known). Because of this, we have been able to do optimizations in this new flow that take advantage of both.

All of those things. Most HLS tools use the CDFG to generate optimized resource bindings and area-aware optimizations.

Author of Calyx here. Good question! Usually, you can use OpenCL based drivers to interface with standard memory interfaces on FPGAs.

ASICs require a lot more work by either packaging on the same chip as a processor or building IO interfaces for their own package.

But again, this notion of "outsiders" is very gatekeepy. There have been substaintial successes in using high-level programming models for hardware design.

The Google VCU paper explicitly mentions using such tools made them faster. All of these is enabled by people looking at problems with a fresh perspective

Odd, it works correctly for me: https://rachit.pl/files/pubs/calyx.pdf

What platform/browser has this problem?

Author of Calyx here. I always find these arguments quite reductive but will nonetheless entertain them.

"Developing Hardware is a solved problem"

For which audience specifically? Maybe if you consider giant teams at large corps pouring in millions. Is it a solved problem for hobbyists, students, people who're just curious? Most people who're curious about software can go play with it in 15 mins. For hardware, it's more like months.

"If you need pseudo-DSL ..."

Weirdly gatekeepy. Why should hardware be only used by experts? There's lot you could've said about it being hard to optimize hardware well (which is challenging with HDLs too) but instead choose this argument.

"You cannot abstract away this engineering task" The goal of research is to try to do things differently. We already know how to build hardware using HDLs, with waterfall models and giant teams. We want to figure out if there are better ways to do it.

The VLSI revolution wouldn't have happened if randos on the internet kept complaining about how "we already know how to do full custom design" and "you cannot abstract physics". We did before, and it changed the world. Let's have some optimism.

You’re thinking of 6110 (advanced programming languages) not 6120

Not quite. This also has the type ‘a -> ‘a:

def nitpick(x): throw “foo”

i have never personally called out anyone anywhere ever

[OP] Yup, that was the intent. I've seen a lot of academic and industrial hand wringing about not wanting to build a compiler because it's an overkill for the solution only to have the people come back 6 months later having built a compiler.

I'm not saying everyone should build a compiler for everything–but when you should build a compiler, you really should bite the bullet and build a compiler.

[OP] Ah, I've just seen a bunch of people showcase "amazing new tools" that are just bad compilers in disguise. State of the art Database query optimizers are good examples of this.

Racket is often heralded as the "programming language programming language" and comes with tons of features to build full blown languages: https://racket-lang.org/

The most complete language/ecosystem that really showcases Racket's capabilities is Rosette IMO: https://github.com/emina/rosette/

Author here.

CS does progress remotely—the publishing model in CS allows authors to easily and openly distribute our papers by putting them up on arvix and our webpages which doesn’t seem to be true of physics journals.

The post is directed to solving the problems of networking. It doesn’t say anything about the orthogonal problem of open access of research.

Author here.

- not really. I have a bunch of experience writing ocaml. I wouldn’t ascribe any good technical reason to this. A lot of research prototyping is finding something you enjoy writing rather than finding the optimal thing to use. Often you’re the only person working on it over the course of many years.

The part you quoted is a part of a thought experiment. The author is explicitly saying that Verilog is _not_ an ISA:

> By way of contradiction, let’s imagine what it would look like if RTL were playing each of these roles well.

The point of this section was to point out that the set of people who use FPGAs as accelerators (a la MSFT catapult) use it with the ISA abstraction: they don’t want to care about he timing, they just want to get the dataflow graph to accelerate the computation.

Disclaimer: I work with the author of the article on acceleration architectures and languages.

Author here. Acceptance criteria are hard to lock down, especially in new projects. The whole point of research is to explore domains and to expect a lot of dead ends.

I’m unsure what a concrete acceptance criteria will look like given that we want to encourage researchers to explore.

Author here. I do recognize that slack has thread by that doesn’t make it easy to refer to an exact thread like email does.

I’m looking for something like a “named thread” which the Twist Chat app has, but is unfortunately not the preferred means of communication in my group.

Question as a Verilog novice. The timescales for execution vs compilation of large-ish programs seem quite different (you’d have multiple simulations done by the time you finish compiling). If this is the case then I’d probably would like to iterate to a new design right after a simulation. Does this tool build some sort of caching for the compilation process which can quickly recompile the design after minor changes?

Several universities still teach racket as an intro language. Ex: Brown, Northeastern, Northwestern, etc.

The authors of Racket specially avoid arguments about teaching language X in introductory CS. The pedagogy and curriculum are significantly more factors in effectively teaching CS [1]. The design of Racket with its restricted languages reflects that.

[1] https://www.janestreet.com/tech-talks/curriculum-design/

Both promises and generators can be used to implement delimited continuations.

Furthermore, there is already a compiler that implements first class delimited continuations in JavaScript: http://stopify.org

The project implements the control operator (which can implement other operators like call/cc). The research paper linked on the website talks about how control is implemented.

Take a look at https://github.com/plasma-umass/stopify

We can do it for general JS programs. If you are willing to compile Python to JS, you can transparently use our compiler to get heap bounded stacks.

This is a cool hack. Our project (Stopify.org) can do this transformation on source JS programs and automatically give you heap bounded stacks transparently.

A cool result of doing this in JavaScript is that any language that compiles to JavaScript (python, ocaml, Scala, c++, clojure...) can transparently get heap bounded stacks by just using our compiler.

For some more examples, look at pyret (pyret.org) that also supports heap bounded stacks. (In fact, we were able to strip out the Pyret compiler and just use Stopify to get all these benefits)

Not really. Naively doing something like that will kill performance, not to mention that you have to be really careful not to mess up inserting setTimeout calls.

Stopify reifies the runtime stack and occasionally yields to the browser through a setTimeout call. Once the yields back control, it can restore the stack and resume computation.