synthos

You can get 900 MHz designs on FPGAs, but yes you need very good engineers and patience to get that.

Yes SRAM is limited but that's more of a ram-process limitation than a limitation of FPGA

Maybe spell checking for prompt text box would save a few bucks

Isn't this solving a subproblem of the overall issue of uncompressed tool call polluting context?

Furthermore, this could be compressed even further with a dynamic legend of every UUID in the context. So UUID@Bravo and UUID@Delta would be the actual symbols in the context but dynamically replaced when calling tools.

How much does your data privacy cost?

Regarding AVX: could rust be compiled with different symbols that target different x64 instruction sets, then at runtime choose the symbol set that is the more performant for that architecture?

> First Revision - Completed with minimal human contribution (auto-accept mode) > > Second Revision - Planned with increased human-in-the-loop involvement

At least 'minimal human contribution' in the first revision. So scan read it as it revised the book.

I do find it amusing to think that people might just ask an AI to summarize the book instead of actually reading it. Maybe even 'review' it as well.

The future will have authenticity in short supply

> Compilers are not yet rewriting data structures and algorithms based on microarchitecture.

Afaik mojo allows for this with the autotuning capability and metaprogramming

What data type/precision? How much parallelism versus iterative? Is this fully in fabric or part of a SoC? Easy to get mired in many details.

HW design has so many degrees of freedom which makes it fun but challenging.

What specific topics are you trying to address with this?

Newton Raphson could be used to calculate a reciprocal. (in a bit width larger than 8). If starting from a good reciprocal approximation, convergence to bit accurate reciprocal should not take many iterations. Then multiply the reciprocal with the numerator to perform the divide

I worked on an automotive FMCW LiDAR that didn't quite make it to market. Cool technology but it was difficult to scale the cost down, which is pretty important for automotive. Margins are very low in that market

Does anyone have a good summary of the Buck(2) track?

It's also, if not more so, a factor of transistor voltage. 1.1V transistors are less prone to upset events than 0.7V. It's possible (assumption, here) that some 3+ volt circuits are still used for critical components of the system

You could probably post it on http://fpgajobs.com/

ARM also recently entered a partnership with Untether to collaborate on low power AI inference for automotive

Hi, Could you please elaborate on your original problem?

The binaries your Bazel system built could not be run unless the runtime environment matched the build environment?

It's a perfect time for Matt Colville's MCDM RPG to be announced. It's on backerkit and people are clearly eager for something different. The crowdfunding is at 4x funding and climbing

Definitely buybait and a shame that a blatant advertisement has made to YC news front page. What's next? Novelty toothpaste for nerds?

Sounds like highly functional personality disorder or manic depression

If there _was_ a good reason to fire Sam, and the board had appropriately and clearly communicated their decision, I think less of the staff would have signed a the petition to walk. From the public's perspective, and probably most rank and file employees, this decision came from left field and had no logic behind it. The waffling and back peddling that followed certainly didn't help perception

Maybe one day, Mojo

nod.ai was just acquired by AMD for a chunk of money. I expect they hope to find a similar exit once they can show an end-to-end product: Take a model written in Pytorch, upcast it to mojo, and put it through their unified compiler stack to accelerate on <hardware>

I think LiFi or something similar has the great potential for VR/AR headset connectivity. With a high bandwidth, low latency link, you could have an untethered experience without the weight and heat of compute and processing in the headset.

To really optimize for latency, perform read lookup (and maybe write slot resolving) before the entire UDP packet is fully buffered and checksum verified.

Interesting, seems like it's very similar to Modular's runtime portion of their business case

> Many Canadian aerospace engineers have never forgiven the government for dismantling Avro Canada’s CF-105 Arrow, a billion-dollar project that, on October 4, 1957—the same day that Russia sent the world’s first satellite into orbit—rolled out the fastest supersonic jet the world had ever seen.

Not just aerospace engineers, but if you ask just about any Canadian and we're all still super sour about this.

Xilinx's AI has a dedicated AI accelerator in the versal so calling it taking advantage of FPGA isn't quite accurate. It's really another chip that happens to be copackaged with the FPGA

I agree that section is a bit confusing. The takeaway is that there are two 4bit formats they're using for weight compression E3M0 and E2M1.