(In other words, my daddy bought me a C64 in the eighties. ;-))
8,047 karma · joined March 15, 2012
(In other words, my daddy bought me a C64 in the eighties. ;-))
While P3 is superscalar, it could only execute about 0.9 instructions per cycle on average. Of course you can optimize for it and get better results in certain cases.
Most Xtensa scalar instructions take just 1 clock, branches 3 for taken, 1 for not taken. So 0.7-0.8 instructions per clock is a reasonable estimate. Assuming of course code is executing from SRAM.
Xtensa's FPU is slow, and it lacks divide and square root instructions. Clock for clock, P3 probably outperforms it by 3-4x. It also lacks 64-bit floats.
Or perhaps you want to argue that everything is running "normal" instructions. Be it a hardware video decoder or a GPU.
Although so far I'm mostly happy with Apple products. Happier than with any Windows laptops.
(But damn if I encounter a bug or an issue. Just reporting those have made hordes of Apple fans attack me, in response to a standard technical bug report.)
According to Musk, 0.5 mach max speed.
He also said it can corner better than any car in the world due to massive downforce. And that it'll be in production in 2028.
We'll see.
If only he just stuck to tech.
At this point you can be talking about 600 kB on a DOS machine. Sky is the limit on modern systems.
That said, typical inner loops of that era demos were pretty small, usually 20-200 byte range, IIRC.
Pre-cache era demos often had huge unrolled self-modifying speedcode inner loops, but that's another matter.
Even with a cycle accurate CPU you'd still have a lot of variation caused by the motherboard chipsets, DRAM speeds, cache chips and graphics cards.
Tseng ET4000 was on a completely different level than something like Cirrus Logic CL-GD510 or heaven forbid, Oak Technologies card.
If the era appropriate PCs had huge variations, what extra does cycle accuracy really bring at this point? The same PC demo could perform very differently on two 486DX2 66 MHz PCs.
The results were indeed multimodal.
All I wanted was to have a reproducible benchmark to see how the code changes affected performance over time.
Additionally I avoided core 0, because it was the noisiest and did some cgroups core pinning for the test workload.
There were zero page faults during the test runs and the CPU core was uncontested by other threads.
I think in 2008 CPUs were not so crazy about power and heat management.
I tried to fix it by switching hyperthreading off, playing with the scaling governor, boost, setting a CPU frequency to no avail. The jitter was too much and the results were not reproducible, so I just gave up.
Of course your mileage may vary; this was on an AMD Zen 3 CPU.
Even the latest rev? Can you elaborate a bit?